1. Field of the Invention
The present invention relates to a calculation system of fault coverage and a calculation method of fault coverage for large scale integrated circuit (LSI), particularly for system LSI or system on chip (SOC).
2. Description of the Related Art
In order to evaluate quality of an LSI test, a fault model has been assumed corresponding to a logical configuration inside an LSI, then a rate of fault detection has been calculated by simulation using a test pattern produced for the LSI test, and then the quality of the test pattern has been evaluated (estimated). A typical fault model includes a “net stuck-at fault model” which assumes that one of connection wiring between basic cells inside the LSI is fixed to either power supply potential (VDD) or ground potential (GND) of the LSI. A proportion of the number of detected faults from among the total number of assumed faults is referred to as fault coverage. This fault model is one of the simplest models, which has a great advantage of easy of calculating the fault coverage. In addition, this fault model can reasonably explain a correlation with a defect level of shipped LSI samples in the market. However, this fault model treats a fault on a connection wire extending across a wide range inside the LSI and a fault on a wire extending across a narrow range inside the LSI equally as one fault. Nevertheless, incidences of defects which cause faults are various and strongly dependent on such layout elements in actual devices, and the traditional fault coverage has not corresponded to such a fact. In a recent advanced LSI process with much small metal wire pitch, it is very important to take an influence of layout elements into account to further enhance test quality. Accordingly, the fault coverage according to the rate of the number of simply detected faults from among the number of the assumed faults has a serious problem.
Basically, the connection wires (the nets) can be categorized into the following two types:    i) single directional connection wires adopting a configuration of connecting one output terminal of a basic cell to input terminals of a plurality of basic cells; and    ii) single directional and bidirectional connection wires adopting a configuration of connecting output terminals of a plurality of basic cells to input terminals of a plurality of basic cells.
Meanwhile, the stuck-at fault model, which is prevalent as the fault model for evaluating the fault coverage of the test pattern by assuming certain faults in the LSI, internal nodes in logical circuits inside the LSI, and the like and by calculating the rate of the faults to be detected by the test pattern configured to test operations of the LSI with the fault simulation technique, includes the “net stuck-at fault model” and a “pin stuck-at fault model”. The net stuck-at fault model is a fault model which assumes that each connection wire (an internal node) inside an LSI is fixed to power supply potential or ground potential. A fault fixed to GND (the ground potential; logic 0) is called a “stuck-at 0 fault” and a fault fixed to VDD (the power supply potential; logic 1) is called a “stuck-at 1 fault”. Meanwhile, the pin stuck-at fault model is a fault model which assumes that each input terminal and output terminal (pins) of an LSI and of a basic cell inside an LSI is fixed to power supply potential or ground potential, wherein a fault fixed to GND (the ground potential; logic 0) is called a “stuck-at 0 fault” and a fault fixed to VDD (the power supply potential; logic 1) is called a “stuck-at 1 fault”. Moreover, fault simulation configured to define a net stuck-at fault of the internal node being fixed to “0” or “1” as an assumed fault is known to be relatively easy to calculate, and fault coverage thus obtained is known to have a considerably high correlation with a rate of faulty products which are mixed in “fault-free” products after screening by use of a test pattern, and with a defect level of LSI chips in the market after shipment. Therefore, the fault simulation defining the net stuck-at fault as the assumed fault has been predominantly.
However, as the process design rules become finer, there are more faults of open defects in which minimum-sized vias (contacts for connecting sets of metal wires which are vertically adjacent to each other) are not formed properly, for example. Here, the net stuck-at fault model has a problem in that the model cannot discern detection of such open defects. In other words, since only two stuck-at faults are defined with respect to each net in the case of the net stuck-at fault model, the model cannot detect which part of a signal path in the net is activated and detected when a fault has been detected. Accordingly, there is a risk that a defect in a minimum-sized via (hereinafter referred to as a minimum via) on the path which is not actually activated may remain undetected. For this reason, the pin stuck-at fault model has been gradually adopted along with the advance of the LSI processes.
In the bidirectional signal wire, outputs of a plurality of tristate buffers are generally connected to a plurality of terminals of basic cells which applies the bidirectional signal wire as inputs. Here, the tristate buffer is a buffer circuit which includes a high impedance state in addition to high level and low level output states. A signal transmission in such bidirectional signal wire is configured such that one tristate buffer always performs output, and outputs of the rest of the tristate buffers are set to a high impedance state, and usually the output is transmitted as a signal through any of the input terminals thereof. Therefore, in the recently popularized pin stuck-at fault model, it is difficult to determine accurately how large a layout region has been tested in the bidirectional signal wire by an applied test pattern, unless a path from an output to an input is correctly specified. However, the evaluation equipment cannot correctly specify the path from the output to the input.